1. Field of the Invention
This invention relates to clock systems employed to synchronize or to time the operation of data processors, logic circuits and input-output units associated with electronic data processing systems. More particularly, this invention relates to a switching circuit for selecting one of a plurality of normally operable asynchronous oscillators employed in timing circuits so as to assure synchronization and to avoid metastability.
2. Discussion of the Prior Art
It is well known that two computers or elements of a complex data processing system which attempt to communicate with each other in a random asynchronous manner are susceptible of creating a metastable condition. For purposes of this invention, a metastable condition is defined as an attempt to change the state of a logic element before the element has had time to become stable or enabled sufficiently to accept or sense the change signal. This creates a condition which will not assure that the desired output is correct. The output of a logic element which is in a metastable condition may be correct or incorrect.
In theory, two viable alternatives have been suggested to circumvent the problem of metastability and interface synchronization. First, permit the parts of the system to remain nonsynchronous and employ sampling techniques which identify time regions in which metastable conditions do not exist. This first approach creates a time lag which is unacceptable to high speed computing systems. The sampling circuits for such a complex system may become costly and difficult to implement.
An alternative approach has been to synchronize all of the interfaces of the components in the system and to create clocking schemes which will guarantee that metastable regions cannot occur. This alternative approach has been implemented is Sperry Univac's distributed processing systems and is described in U.S. Pat. No. 4,021,784.
In the above-identified Sperry Univac system, there are a plurality of clocks associated with a plurality of computers. Each computer has associated therewith, input/output equipment and its own clock. Logic circuits are employed to selectively connect only one of the asynchronous clocks to the total system. The logic circuits are provided with individual timed output lines connected to the central processing units and to the individual input/output units. During a switching operation, all timed outputs are temporarily blocked for a predetermined number of computer cycles. The previous clock is blocked and the new clock is subsequently enabled at least one or more cycle times later. When several clocks are present in a distributed processing system, they are located at the individual processing units and thus are a substantial distance from each other, and such precautions are required as well as being justified.
When a central processing system is provided with a similar frequency back-up clock which is asynchronous with the master clock, or when the central processing system is provided with a substantially slower or faster asynchronous clock, they can be located at or near the master clock. In a typical system having a plurality of asynchronous clocks of different frequencies, the slower clocks are employed for maintenance purposes and may be on the same circuit board.
When a plurality of asynchronous clocks are located close enough to each other to be synchronized or substantially synchronized, the compensation for cable delays can be ignored or easily overcome.